Electronics below 10 Nm

This chapter reviews prospects for the development and practical introduction of ultrasmall electron devices, including nanoscale field-effect transistors (FETs) and single-electron transistors (SETs), as well as new concepts for nanometer-scalable memory cells. Physics allows silicon FETs to be scaled down to ∼3 nm gate length, but below ∼10 nm the devices are extremely sensitive to minute (sub-nanometer) fabrication spreads. This sensitivity may send the fabrication facilities costs (high even now) skyrocketing, and lead to the end of the Moore Law some time during the next decade. Lithographically defined SETs can hardly be a panacea, since the critical dimension of such transistor (its single-electron island size) for the room temperature operation should be below ∼1 nm. Apparently, the only breakthrough that would allow to make 1-nm-scale electron devices practical, would be the introduction of “CMOL” hybrid integrated circuits that would feature, in addition to an advanced CMOS subsystem, a layer of ultradense molecular electron devices. These devices would be fabricated by chemically-assisted self-assembly from solution on few-nm-pitch nanowire arrays connecting them to the CMOS stack. Due to the finite yield of molecular devices and their sensitivity to random charged impurities, this approach will require a substantial revision of integrated circuit architectures, ranging from defect-tolerant versions of memory matrices and number crunching processors to more radical solutions like hardware-implemented neuromorphic networks capable of advanced image recognition and more intelligent information processing tasks.